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E2C0017-27-Y2
Semiconductor MSC1201-XX
Semiconductor
This version:MSC1201-XX Nov. 1997 Previous version: Jul. 1996 www..com
60-Bit VFD Tube Driver with Digital Dimming and PWM Conversion Function
GENERAL DESCRIPTION
The MSC1201-XX is a 1/2 duty vacuum fluorescent display tube driver implemented in Bi-CMOS technology. This LSI consists of 64-bit shift registers, 64 latches, PWM conversion circuit, a digital dimming circuit, 30-segment driver and 2-grid driver. As the MSC1201-XX has both a digital dimming circuit and a PWM conversion circuit which converts PWM signal for lamp dimming control to PWM signal for VFD tube dimming control, the dimming control can be realized without any external circuit. The interface with a MCU can be done only with 3 wires (CS, DATA and CLOCK signals). Also, DATA and CLOCK signal lines can be shared with other peripherals because of chip select function by CS signal. For the general purpose code, the code number is -01. (Product name: MSC1201-01GS-2K) For a custom code, the code number will be ordered at any time.
FEATURES
* Single supply voltage : VDD = 8 V to 18 V (built-in 5 V logic regurator) * Operating temperature range : Ta = -40C to +85C * 30-segment driver outputs (IOH = -6 mA at VOH = VDD - 0.8 V) * 2-grid pre-driver outputs (IOH = -30 mA at VOH = VDD - 0.8 V) * Built-in digital dimming circuit (11-bit resolution) * Built-in oscillation circuit (external R and C, fOSC = 2.0 MHz) * Built-in Power-On-Reset circuit. * Lamp PWM signal AE Buil-in PWM conversion circuit for vacuum fluorescent display tube. * Built-in RC Oscillation (external R and C) * Correspondence between shift register and output segment is settable optionally using built in mask programmable 30 30 PLA. * Package : 44-pin plastic QFP (QFP44-P-910-0.80-2K)(Product name: MSC1201-XXGS-2K) xx indicates the code number
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BLOCK DIAGRAM
SEG1 5V VDD GND 5 V Reg & POR Circuit POR CS DATA CLOCK 30-Segment Driver
SEG30
GRID1
GRID2
2-Grid Driver
30 30 PLA Matrix
Control Circuit
Multiplexer
Latch S1 D CK 64-Bit Shift Register D48-59 R POR M3 M2 M1 M0 Mode Selector S1 S2 S3 S4 OSC0 OSC1 RC OSC Timing Generator R POR PWM Conversion Circuit R POR Digital Dimming Circuit R S2 POR S2 Selector S3 S4 INH Test Mode DATA OUT
PWMIN VK
TEST1
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INPUT AND OUTPUT CONFIGURATION
* Schematic Diagrams of Logic Portion Input * Schematic Diagrams of Logic Portion Input Circuit 1 Circuit 1
VDD (5V Reg.) VDD TEST1 INPUT INH (5V Reg.)
GND
GND
GND
GND
* Schematic Diagrams of Logic Portion Output * Schematic Diagrams of Driver Output Circuit Circuit
(5V Reg.) (5V Reg.) VDD VDD
OUTPUT
OUTPUT
GND
GND
GND
GND
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PIN CONFIGURATION (TOP VIEW)
44 SEG21 43 SEG20 42 SEG19 41 SEG18 40 SEG17 39 SEG16 38 SEG15
37 SEG14
36 SEG13
35 SEG12
34 SEG11
SEG22 1 SEG23 2 SEG24 3 SEG25 4 SEG26 5 SEG27 6 SEG28 7 SEG29 8 SEG30 9
33 SEG10 32 SEG9 31 SEG8 30 SEG7 29 SEG6 28 SEG5 27 SEG4 26 SEG3 25 SEG2 24 SEG1 23 DATAOUT
DATA 20 INH 21 PWM IN 22
GRID1 10 GRID2 11
VDD 12
TEST1 13
VK 14
OSC1 15
OSC0 16
GND 17
CS 18
44-Pin Plastic Package
CLOCK 19
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PIN DESCRIPTIONS
Pin 1-9 24-44 10, 11 16 15 18 Symbol SEG1-30 GRID1, 2 OSC0 OSC1 CS I/O O O I O I Segment output pin for VFD Grid 1 and Grid 2 output pins for VFD RC oscillation pins. Connect a resistor between OSC1 and OSC0 pin and a capacitor between OSC0 and GND pin. Chip select input. Only when the high level is input to this pin, interfacing with a MCU is available through "CLOCK" and "DATA" pins. Therefore, 2-signal lines of "CLOCK" and "DATA" can be shared with other peripherals. Input which receives display data and digital dimming data from a MCU. Data is shifted in at the rising edge of the shift clock. Serial clock input. Data that is input through "DATA" pin is input and output by synchronization with the rising edge of the serial clock. Serial data output. Data is shifted out at the rising edge of the serial clock with the delay of 64-bit time. This pin is used for cascading this LSI with other drivers such as a LED driver. PWM signal input. Dimming select input. When the high level is input, daylight-mode output duty cycle is about 100% for each grid time for PWM conversion and digital dimming mode. When the low level is input, the dark-mode output duty cycle is determined by the duty cycle of the PWM signal input to PWM IN and the digital dimming output duty cycle is determined by digital dimming data. Blank Display input with a built-in pull-up resistor. When set to "L", all the drivers output "L". When display duly is not controlled by this signal, leave this pin open. Test signal input pin. As this pin is used for shipping test of the LSI, leave open in the normal operation mode. Power Supply Ground Description
20 19 23
DATA CLOCK DATA OUT PWMIN VK
I I O
22 14
I I
21 13 12 17
INH TEST1 VDD GND
I I -- --
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ABSOLUTE MAXIMUM RATINGS
Parameter Supply Voltage Input Voltage Storage Temperature Range Power Dissipation Symbol VDD VIN TSTG PD Condition -- All inputs -- Ta = 85C Rating -0.3 to +20 -0.3 to +6 -65 to +150 0.4 Unit V V C W
RECOMMENDED OPERATING CONDITIONS
Parameter Supply Voltage High Level Input Voltage (1) High Level Input Voltage (2) High Level Input Voltage (3) Low Level Input Voltage (1) Low Level Input Voltage (2) Clock Frequency OSC Frequency Frame Frequency Operating Temperature Range Symbol VDD VIH1 VIH2 VIH3 VIL1 VIL2 fC fOSC FFR Top Condition -- All inputs except OSC0, VK VK OSC0 All inputs except OSC0 OSC0 -- R = 4.7kW, C=22pF fOSC = 2 MHz -- Min. 8 3.8 3.8 4.5 0 0 -- -- -- -40 Typ. -- -- -- -- -- -- -- 2 224 -- Max. 18 5.5 VDD 5.5 0.8 0.5 250 -- -- 85 Unit V V V V V V kHz MHz Hz C
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ELECTRICAL CHARACTERISTICS
DC Characteristics
(Ta = -40 to +85C, VDD = 8 to 18 V) Parameter Hight Level Input Voltage (1) *1 Hight Level Input Voltage (2) *9 Hight Level Input Voltage (3) *2 Low Level Input Voltage (1) *10 Low Level Input Voltage (2) *2 Hight Level Input Current (1) *3 Hight Level Input Current (2) *4 Hight Level Input Current (3) *5 Low Level Input Current (1) *3 Low Level Input Current (2) *4 Low Level Input Current (3) *5 High Level Output Voltage (1) *6 High Level Output Voltage (2) *7 Symbol VIH1 VIH2 VIH3 VIL1 VIL2 IIH1 IIH2 IIH3 IIL1 IIL2 IIL3 VOH1 VOH2 VOH3-1 High Level Output Voltage (3) *8 VOH3-2 VOL1-1 Low Level Output Voltage (1) *6 *7 VOL1-2 VOL1-3 Low Level Output Voltage (2) *8 Power Supply Current VOL2 IDD Condition -- -- -- -- -- VIH1 = 5.0 V VIH2 = 5.0 V VIH3 = 5.0 V VIL1 = 0.0 V VIL2 = 0.0 V VIL3 = 0.0 V VDD = 9.5 V IOH1 = -6 mA VDD = 9.5 V IOH2 = -30 mA VDD = 9.5 V IOH3-1 = -200 mA VDD = 9.5 V Output Open VDD = 9.5 V IOL1-1 = 500 mA VDD = 9.5 V IOL1-2 = 200 mA VDD = 9.5 V IOL1-3 = 2 mA VDD = 9.5 V IOL2 = 200 mA fOSC = 2 MHz, No load Min. 3.8 3.8 4.5 0 0 -5 -80 -60 -5 -0.6 -320 VDD-0.8 VDD-0.8 4 4.5 -- -- -- -- -- Max. 5.5 VDD 5.5 0.8 0.5 5 80 60 5 -0.1 -30 -- -- 6 6 2 1 0.3 0.8 20 Unit V V V V V mA mA mA mA mA mA V V V V V V V V mA
Notes: *1 *2 *3 *4 *5 *6 *7 *8 *9 *10
Applicable to all input pins (except VK, OSC0 pin) Applicable to OSC0 pin Applicable to CLOCK, DATA, CS, VK, and PWMIN pin Applicable to TEST1 Applicable to INH pin Applicable to pins SEG1 to SEG30 Applicable to GRID1 and GRID2 Applicable to DATA OUT pin Applicable to VK pin Applicable to all input pins (except OSC0 pin)
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Semiconductor AC Characteristics
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(Ta = -40 to +85C, VDD = 8 to 18 V) Parameter Oscillation Frequency OSC0 Input Frequency Clock Frequency Clock Pulse Width Data Set-up Time Data Hold Time CS Pulse Width CS Off Time CS Set-up Time CS-Clock Time CS Hold Time Clock-CS Time Data Output Delay Clock-Data out Time SEG & GRID Output Delay from CS Slew Rate (All Drivers) Power-on CS Time Power-off Hold Time Power-on Rise Time Frame Frequency Symbol fOSC fOSCI fC tCW tDS tDH tCSW tCSL tCSS tCSH tPD tODS tR tPCS tPOF tPRZ FFR Condition R = 4.7kW, C = 22pF External input only -- -- -- -- -- -- -- -- -- CL = 100pF CL = 100pF, t = 20% to 80% or 80% to 20% -- When the Unit mounted VDD = 0 V When the Unit mounted -- Min. 1.2 1.5 -- 1.3 1 200 68 30 2 2 -- -- -- 300 5 -- 146 Max. 2.8 2.5 250 -- -- -- -- -- -- -- 1 8 5 -- -- 100 342 Unit MHz MHz kHz ms ms ns ms ms ms ms ms ms ms ms ms ms Hz
PWM Conversion Characteristics
(Ta = -40 to +85C, VDD = 8 to 18 V) Parameter PWM Input Frequency Input Threshold Voltage PWM Input Duty Cycle Symbol fPWM vR dU Condition -- -- -- Min. 176 0.8 20 Typ. 256 2.5 -- Max. 336 3.8 100 Unit Hz V %
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TIMING DIAGRAM
tCSW 3.8V 0.8V tCSS tCW 3.8V 0.8V fC tCW tCSH tCSL
CS
CLOCK
tDS 3.8V 0.8V
tDH
tDS
tDH
VALID
VALID
DATA
Fig. 1 Data Input Timing
tCW 3.8V 0.8V
tCW
CLOCK
tPD DATA 3.8V 0.8V
tPD
Fig. 2 Data Output Timing
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TIMING DIAGRAM (Continued)
VDD
8V tPRZ tPOF tPCS 3.8V 0.8V
CS
Fig. 3 Power-On Timing
tCSW CS 3.8V 0.8V tODS 80% SEG1-30 GRID1, 2 20% tR tODS tR
Fig. 4 SEG & GRID Driver Output Timing
PWM Frequency (fPWM) Input Threshold Voltage PWMIN A B
Duty Cycle dU = A/(A+B)
Fig. 5 PWM Input Waveform
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FUNCTIONAL DESCRIPTION
Power-On-Reset The status of the internal circuit after power-on reset is as follows; 1) Shift registers and latches are reset. 2) PWM conversion mode is selected. DATA Input Data input is available only when the high level is applied to the "CS" pin. Input data is shifted into shift registers through "Data" pin at the rising edge of the shift clock. The data is automatically loaded to latches at the falling edge of "CS" signal. When M0 = "0", input data should include display data (total of 64 bits data should be input.) and when M0 = "1", input data should exclude display data (Total of 16-bit data should be input.) [Data Format] 1) Display Data Input Mode Input Data : 64 bits VF Display Data : 60 bits Mode Select Data : 4 bits
First In Bit 64 63 62 53 52 51 M2 50 M1 49 48 3 D2 Display Data 2 D1 1 D0
D59 D58 D57 Display Data
D48 M3
M0 D47
Mode Data
2) Segment outputs/Shift Registers Bit Correspondence Table The content of the table depends on a PLA code. This table is modeled on the general purpose code of -01. Segment output positions can be changed dependent on the PLA code, but the segment-bit correspondence cannot be changed.
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Bit
8 8
7 7
6 6
5 5
4 4
3 3
2 2
1 SEGn 1 GRID1
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 GRID2
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Semiconductor 3) Digital Dimming Data Input Mode Input Data : 16 bits Digital Dimming Data : 11 bits Mode Select Data : 4 bits
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Bit
64 xx
63 11 MSB
62 10
61 9
60 8
59 7
58 6
57 5
56 4
55 3
54 2
53 1 LSB
52 M 3
51 M 2
50 M 1
49 M 0
First in
Dimming Data (MSB) X X X X 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 INPUT DATA 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 0 0 0 1 0 0 0 1 (LSB) 0 1 0 1
Mode Data DUTY CYCLE 0/2048 1/2048 2032/2048 2032/2048
4) Function Mode
Mode S1 S2 S3 S4 S5 S6 M3 0 0 0 0 0 0 M2 0 0 0 0 1 1 M1 0 0 1 1 0 0 M0 0 1 0 1 0 1 Display Data Input Digital Dimming Data Input PWM Conversion Select & Display Data Input PWM Conversion Select Digital Dimming Select & Display Data Input Digital Dimming Select Function
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In the PWM conversion mode, "lamp PWM", which is used for dimming control of back-light for instrument clusters or other displays, is used to generate the PWM signal for VFD tube dimming control. The lamp PWM input to "PWM IN" pin is converted to PWM signal for VFD tube with a built-in PWM conversion look-up table (User-Programmable Mask ROM). The duty cycle of the lamp PWM is defined as follows:
PWMIN
A
B
5V
PWM Input Frequency = 256 80Hz Duty Cycle = A / (A+B)
Note: The duty cycle of the lamp PWM signal is measured with a reference point of 2.5 V typ. As the reference point of 2.5 V is the threshold voltage of "PWM IN" pin, it deviates to some value between 0.8 V and 3.8 V due to process parameter deviation. Therefore, the PWM conversion error increases as the rise/fall time of the lamp PWM increases. GRID/SEG Driver Operation and Digital/Analog Dimming Operation Figure 6 shows an output timing of the GRID and SEG Driver when the VK is "H" level. Output timings of the GRID and SEG drivers are shown in figure 7 for the digital dimming mode operation in figure 8 for the PWM conversion mode operation. (1) GRID and SEG drivers output timings when VK = "H"
1 Frame (4096-bit times) fFR GRID1
GRID2 2032-bit times 6-bit times SEG1-30
16-bit times
2038-bit times
10-bit times
Fig. 6 GRID and SEG Output Timing (VK = "H") Note: One bit time = 2/fOSC = 1 ms typ.
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(2) GRID and SEG driver output timing when VK = "L" and in Digital Dimming Mode.
1 Frame (4096-bit times) fFR GRID1
GRID2 Max. 2032-bit times 6-bit times SEG1-30
16-bit times
Max. 2038-bit times
10-bit times
Fig. 7 GRID and SEG Output Timing (digital dimming mode) Notes: * The above indicates the timing for the digital dimming mode with the duty cycle of 2032/2048 at VPARK = "L" level. * The On-times for GRID and SEG are specified with the 11 bits of the digital dimming data. * One bit time = 2/fOSC = 1 ms typ. (3) GRID and SEG driver output timings when VK = "L" and in PWM Conversion Mode
1 Frame (2048-bit times) fFR GRID1
GRID2 Max. 256-bit times 3-bit times SEG1-30 Max. 259-bit times
8-bit times
Fig. 8 GRID and SEG Driver Output Timing (PWM conversion mode) Notes: * The above indicates the GRID and SEG Drivers Timing when the PWM conversion mode at VK = "L" level is selected. * One bit time = 4/fOSC = 2 ms typ. 14/20
Semiconductor PWM Conversion Table MSC1201-01
STEP No. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 LAMP PWM DUTY CYCLE 100.00% 98.75% 97.50% 96.25% 95.00% 93.75% 92.50% 91.25% 90.00% 88.75% 87.50% 86.25% 85.00% 83.75% 82.50% 81.25% 80.00% 78.75% 77.50% 76.25% 75.00% 73.75% 72.50% 71.25% 70.00% 68.75% 67.50% 66.25% 65.00% 63.75% 62.50% 61.25% 60.00% VF PWM DUTY CYCLE 12.50% 12.30% 12.11% 11.91% 11.72% 11.52% 11.33% 11.13% 10.94% 10.74% 10.55% 10.35% 10.16% 9.96% 9.77% 9.57% 9.38% 9.18% 8.98% 8.79% 8.59% 8.40% 8.20% 8.01% 7.81% 7.62% 7.42% 7.23% 7.03% 6.84% 6.64% 6.45% 6.25% STEP No. 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 LAMP PWM DUTY CYCLE 58.75% 57.50% 56.25% 55.00% 53.75% 52.50% 51.25% 50.00% 48.75% 47.50% 46.25% 45.00% 43.75% 42.50% 41.25% 40.00% 38.75% 37.50% 36.25% 35.00% 33.75% 32.50% 31.25% 30.00% 28.75% 27.50% 26.25% 25.00% 23.75% 22.50% 21.25% 20.00%
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VF PWM DUTY CYCLE 6.05% 5.86% 5.66% 5.47% 5.27% 5.08% 4.88% 4.69% 4.49% 4.30% 4.10% 3.91% 3.71% 3.52% 3.32% 3.13% 2.93% 2.73% 2.54% 2.34% 2.15% 1.95% 1.76% 1.56% 1.37% 1.17% 0.98% 0.78% 0.59% 0.39% 0.20% 0.10%
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Semiconductor PLA Code Table MSC1201-01
SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
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PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN
24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 1 2 3 4 5 6 7 8 9
BIT 1, 31 BIT 2, 32 BIT 3, 33 BIT 4, 34 BIT 5, 35 BIT 6, 36 BIT 7, 37 BIT 8, 38 BIT 9, 39 BIT10, 40 BIT11, 41 BIT12, 42 BIT13, 43 BIT14, 44 BIT15, 45 BIT16, 46 BIT17, 47 BIT18, 48 BIT19, 49 BIT20, 50 BIT21, 51 BIT22, 52 BIT23, 53 BIT24, 54 BIT25, 55 BIT26, 56 BIT27, 57 BIT28, 58 BIT29, 59 BIT30, 60
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Pin Name SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15
Output BIT 1,31 BIT 2,32 BIT 3,33 BIT 4,34 BIT 5,35 BIT 6,36 BIT 7,37 BIT 8,38 BIT 9,39 BIT 10,40 BIT 11,41 BIT 12,42 BIT 13,43 BIT 14,44 BIT 15,45
Pin Name SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30
Output BIT 16,46 BIT 17,47 BIT 18,48 BIT 19,49 BIT 20,50 BIT 21,51 BIT 22,52 BIT 23,53 BIT 24,54 BIT 25,55 BIT 26,56 BIT 27,57 BIT 28,58 BIT 29,59 BIT 30,60
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APPLICATION CIRCUITS
(1) Digital Dimming Mode
1/2 Duty VF Tube
12 V
SEG1 VDD GND
SEG30
G1,G2
CS Microcontroller DATA CLOCK OSC1 MSC1201-XX
OSC0
VK PWM IN
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Semiconductor (2) PWM Conversion Mode
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1/2 Duty VF Display Tube
SEG1 12 V VDD GND
SEG30
G1 G2
CS Microcontroller DATA CLOCK OSC1 OSC0 Daylight Mode "1" Dark Mode "0" Illumination Switch Illumination Lamp Dashboard Lamp Lamp PWM Signal MSC1201-XX
5V
VK PWMIN
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PACKAGE DIMENSIONS
(Unit : mm) QFP44-P-910-0.80-2K
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 0.41 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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